Menus

File

	Ctrl+ | ⌘+
File > New	N	Create a new window.
File > Open...	O	Open a Project.
File > Add as block...		Add a Project as a block.
File > Collections		See Collections.
File > Plugins		List of available plugins.
File > Save	S	Save the current Project.
File > Save as...	Shift+S	Save the current Project in a new file.
File > Export...		Export multiple output files.
File > Documentation.		View built-in documentation.
File > About		Information about the application.
File > Quit	Q	Exit the application.

Edit

	Ctrl+ | ⌘+
Edit > Undo	Z	Undo the last change.
Edit > Redo	Y | Shift+Z	Revert the last undo.
Edit > Cut	X	Cut selected blocks.
Edit > Copy	C	Copy selected blocks.
Edit > Paste	V	Paste copied blocks.
Edit > Clone	Shift+V
Edit > Select all	A	Select all the blocks.
Edit > Fit content	1	Fit the content into the screen.
Edit > Preferences		See Preferences.
Edit > Project information		View/edit Project metadata.

Note

Export files/formats are: Verilog, PCF, Testbench, GTKWave, BLIF, ASC and Bitstream.

Footer

	Ctrl+ | ⌘+
Boards		Change the current Board and settings.
Verify	R	Check the generated verilog code.
Build	B	Synthesize the bitstream from the design.
Upload	U	Upload the bitstream to the FPGA.
View command output		Show output of the latest executed command.
Device resource usage		Figures provided by synthesis and P&R tools.

Note

Upload will trigger Synthesize, if required.