Upload a bitstreamΒΆ
Open a project
Go to Edit > Open... and select an .ice file.
Verify the project
Go to Tools > Verify.
This option checks the generated verilog code using
apio verify
.Build the project
Go to Tools > Build.
This option generates a bitstream using
apio build
.Upload the project
Connect your FPGA board and press Tools > Upload. This option uses
apio upload
.
After executing Tools > Verify, Tools > Build or Tools > Upload you can see the executed command and the output in a new windows opened from View > Command output.
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