Upload a bitstreamΒΆ

  1. Open a project

    Go to Edit > Open... and select an .ice file.

  2. Verify the project

    Go to Tools > Verify.

    This option checks the generated verilog code using apio verify.

  3. Build the project

    Go to Tools > Build.

    This option generates a bitstream using apio build.

  4. Upload the project

    Connect your FPGA board and press Tools > Upload. This option uses apio upload.


After executing Tools > Verify, Tools > Build or Tools > Upload you can see the executed command and the output in a new windows opened from View > Command output.